Electronic memories can suffer from faults in a variety of modes. For example, in a stuck-at fault (SAF), a memory cell can remain constant at logical 0 or logical 1. In another example of a failure mode, in a deceptive read destructive fault (DRDF), a memory cell can flip state during a read operation but return an original correct value. Similarly, there are numerous other failure modes.
A built-in self-test (BIST) allows an electronic memory to be tested. The electronic memory can be subjected to the BIST either periodically, upon power-up, in response to an external signal or condition, or under other circumstances. A BIST test algorithm in the BIST typically comprises many elements, referred to as March elements. A March element includes a sequence of operations, for example write-0, write-1, and read-1, which are applied to a given memory cell before proceeding to a next memory cell. The BIST can proceed from memory cell to memory cell in an increasing order of addresses, or in a decreasing order of addresses, or in some arbitrary order of addresses. A sequence of March elements is defined as a March test.
There exists a notation that describes the March test as follows. A complete March test is delimited by a ‘{ . . . }’ parenthesis pair whereas a March element is delimited by a ‘( . . . )’ parenthesis pair. The March element can include a plurality of following operations, with notations as indicated: Increase address order, notated by . Decrease address order, notated by . Move through a sequence of addresses in an arbitrary manner, notated by . Write logical 0, write logical 1, read logical 0, read logical 1, notated respectively by W0, W1, R0 and R1. As an example of notation, the March test {(W0),  (R0,W1),  (R1,W0)} instructs to write 0 to memory addresses in some arbitrary or pre-defined sequence, then to each memory cell in the increasing order of addresses read 0 and write 1 before going to the next memory cell, and finally to each memory cell in the decreasing order of addresses read 1 and write 0 before going to the next memory cell. It is the convention that when symbols  and  appear in one formula, the symbols represent address sequences that are exact reverses of each other. It is also convention that ˜X represents logical opposite of a value represented by Boolean variable X.
A typical apparatus for BIST includes a finite state machine (BIST-FSM), an address generator, a data generator, and a programmable test algorithm register (TAR). The TAR holds information relating to the March elements, namely an addressing direction, an addressing type, an addressing mode, an operation code (that is, a sequence of read or write operations to be applied to each memory cell) and a pattern type (that is, a code that represents data to be written to the memory cells). The contents of the TAR are referred to as test algorithm, and are generated using a software tool that resides outside the BIST. The data generator creates patterns of data to be written to the memory cells during the test. Test data created by the data generator is referred to as a background pattern (BP). The BP can be pre-defined or programmed. The address generator creates signals along an address bus that locate address of a memory cell to be tested and thereby makes the memory cell ready for read or write.
Upon triggering of the BIST, the BIST-FSM of the apparatus reads data from the TAR, and thereby selects the addressing type, the addressing sequence, the code corresponding to the background data pattern, and the sequence of read or write operations. Based on the pattern type, the data generator generates the test data. Based upon the addressing direction, the addressing sequence and the addressing mode, the address generator selects the memory cell to be tested. Based upon the operation code, the test data is applied to the memory cell to be tested. The test algorithms, that is, the contents of the TAR that specify the March tests, are generated using a software tool that resides outside the BIST.
Hence, there is a need for a way to automatically generalize March tests to detect additional kinds of faults.